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Founded in 1999, EE Solutions (EES) is a leading provider of ASIC and System-on-Chip (SoC) design solutions. EES delivers both design and turnkey services to worldwide IC design houses and systems companies. EES has been recognized as high-quality services provider for its engineering background and overseas delivery experience.

EES is proven to provide the best solutions to serve customers with the advanced design technology that meets what our customers need. EES also offers effective design methodologies and a wide range of advanced intellectual property (IP) and professional personnel to help customers step into the nanometer design field. EE Solutions is headquartered in Hsinchu City with representatives in Korea. EES China Corp. is established with headquarters in Shanghai and a branch office in ShenZhen.

Management Team

Jim Su

CEO

  • Jim Su is the President & CEO of EE Solutions. From 1986 through 1998, he was the director and senior manager for Cadence Taiwan, and Cadence Design Systems in San Jose, California. He also serves as board director for Skylan Communications, Shanghai Huajie IC Technologies, Dalian JieMa Technologies and is an advisor for PerfiSANs Networks, Inc. in Toronto, Canada and Dragon Venture, Inc. in Palo Alto, California.
  • He earned his MSEE from the University of Santa Clara, California, completed his MBA program from San Jose State University, and earned his BS from National Chiao Tung University in Hsin-Chu, Taiwan.

PH Chang

Operations VP

  • PH Chang is the VP of Operations in EE Solutions. Prior to joining EE Solutions, he served as Design Manager in Philips from 1986 to 1998 and served as ASIC Design BU Director in Destiny Technology (now is part of Primax) from 1998 to 2002.
  • From 2002 to 2006, Mr. Chang served as CEO of JieMa Technologies in Dalian, China. Prior to joining EES, Mr. Chang served as VP of Engineering in Sunxt in HsinChu, Taiwan.

SK Lin

R&D Div. Director

  • S.K. Lin is the Director of R&D engineering in EE Solutions with more than 15 years of IC design and EDA experiences. Prior to joining EE Solutions, Mr. Lin served in key engineering management position for various companies in Taiwan.
  • Mr. Lin received his Bachelor and Master degrees in Electrical Engineering from National Chiao Tung University, Hsin-Chu, Taiwan.

HC Yang

Program Management Div. Director

  • HC Yang is the director of Program Management, responsible for IC design solution and mass production process control.
  • Before join EES, HC served as critical position in Holtek Semiconductor Inc, Faraday Technology Corporation and Sunplus technology Co. Inc.

Milestone

Established in 1999 with headquarters in Hsinchu, Taiwan
Established a design center in Taipei in 2000• 2001 established US office in San Jose
Established a joint venture company in Shanghai, China in 2001
April 2002 ISO 9001-2000 certification
Established EES China in Shanghai in 2004
Strategic alliance with Arasan Chip Systems in 2007 to promote USB IP and design services in China
In 2008, we supported customers complete specification development, design inductive touch ASICs and mass production. Customers became the only supplier of patented inductive touch screen ASIC in the world, successfully entering the touch screen ASIC market.
In 2009, MIPS and EES cooperated to complete the CPU hard core setting to over 900 Mhz (TSMC 65nm) and began to provide MIPS architecture solutions for semiconductor companies in China and Taiwan.
In 2011, EES cooperated with Korean customers to develop capacitive touch ASICs and successfully entered mass production.
Partnered with customers to develop ultra-low power consumption in 2012 (more than 10 power-offs, less than 1 u A sleep) M0 base ASIC design service, entering digital measurement instrument customers
Cooperated with customers in 2014 to develop high-end test instrument control ASICs, and related customized analog and digital IP, and successfully entered mass production, customer product line and competitiveness
In 2016, EES cooperated with customers to develop DAB ASIC and related customized analog IP, and assisted customers to introduce low-power architecture and design in 55nm process, successfully entering mass production.
In 2018, with the leading RFIP (Zigbee, BLE5, BLES5.1) vendor strategic alliance, completed the first Industrial 4.0 IoT SoC ASIC single chip for customers, including specification, IC design, verification and production. Successfully entered AI/IoT field

Success Stories


    • ▸ Proven track record of on-schedule chip delivery, some of them are most complex ones in the market
    • ▸ Partnering with many solutions providers
    • ▸ Wide selection of IP portfolios
    • ▸ Hands on experiences on most advanced technologies
    • ▸ Tight customer data security control
    • ▸ Responsive local engineering support
    • ▸ Quality driven standard operation procedure
    • ▸ Competitive NRE and unit price
    • ▸ Flexible and customized business models


Design Summary:
  • Process: 180nm LP 1P5M
  • Gate count: 200K
  • Frequency: 30MHz
  • IP :
    • Low noise compactor
    • Power manage unit
    • Ultra low quiescent current power
    • ADC

Status: Tape-out

Design Challenges:
  • Standby current < 1.0uA
  • Noise reduction on RF interface
Design Summary:
  • Process: 180nm GP 1P5M
  • Gate count: 100K
  • Frequency: 30MHz
  • IP :
    • Low noise comparator
    • Programmable gain controller

Status: Mass-production

Design Challenges:
  • Programmable gain controller
Design Summary:
  • Process: 55nm LP 1P7M
  • Gate count: 1M+ 30 Macro
  • Frequency: 100MHz
  • IP :
    • RF macro
    • Low power SRAM

Status: Tape-out

Design Challenges:
  • More than 10 power domains
  • CPF/UPF design
Design Summary:
  • Process: 180nm LP 1P5M
  • Gate count: 20K+ 4Macro
  • Frequency: 1000 MHz
  • IP :
    • LVPECL
    • Ultra low jitter PLL

Status: Tape-out

Design Challenges:
  • Ultra low jitter PLL
  • LVPECL
Design Summary:
  • Process: 180nm LP 1P5M
  • Gate count: 20K+ 20Macro
  • Frequency: 40 MHz
  • IP :
    • Sensor
    • Status: Mass Production
Design Summary:
  • Process: 28nm LP 1P7M
  • Gate count: 2M+ 200Macro
  • Frequency: 333 MHz

Status: Mass Production

Design Challenges:
  • MBIST redundant architecture
  • MBIST diagnosis fail location
  • MBIST gate count reducing
  • Congestion handling of MBIST groups
  • Balance the MBIST gate count and congestion
Design Summary:
  • Technology: 65nm LP 1P6M
  • Clock speed: ~400Mhz

Status: Mass Production

Design Challenges:
  • Multi-power/multi-Voltage design
    • 2 switched power domain, 1 stand-by domain
    • Under-drive power domain timing optimization
  • Muti-Vt library timing optimization
Design Summary:
  • Process: 55nm ULL 1P7M
  • Gate counts: 10M+30 Macro
  • Frequency: 850MHz

Status: Project delivery (MPW)

Design Challenges:
  • Multi-corner/multi-mode optimization
  • Integrated a high speed 850Mhz CPU hardcore
  • Data-cache/Instruction-cache speed is 750Mhz
    • Use skew optimization to achieve over 850Mhz speed
  • Low power flow approach/high speed fusion design
Design Summary:
  • System company in ShangHai
  • Process: 65nm 1P9M
  • Gate counts: ~6M+ ~100 Macro
  • IP:
    • DDRII/ III
    • Video AFE
    • MIPS24Kec
    • Multi-standard decoder
    • LVDS
    • HDMI
    • Video decoder w/ Comb filter
    • Scaler
  • Frequency: 650MHz

Status: Mass production

Design Challenges:
  • Multi-corner/multi-mode optimization
  • Power optimization for heavy power consumption
Design Summary:
  • Process: 90nm 1P7M
  • Gate counts: 450K+40 Macro
  • IP: USB PHY, Audio DAC/ADC
  • Frequency: 100MHz

Status: Mass Production

Design Challenges:
  • Multi-corner/multi-mode optimization
  • Low power flow: Leakage optimization with multi-Vt approach
Design Summary:
  • Process: 90nm 1P7M
  • Gate counts: 500K+42 Macro
  • IP: USB PHY, audio DAC/ADC
  • Frequency: 100MHz

Status:Mass Production

Design Challenges:
  • Multi-corner/multi-mode optimization
  • Low power flow: Leakage optimization with multi-Vt approach
Design Summary:
  • Process: 90LP 1P6M
  • Gate count: 470K+17 Macro
  • Frequency: 120MHz
  • IP :
    • Multi-voltage IO,
    • Bandgap
    • ARM11 hardcore

Status: Mass Production

Design Challenges:
  • Digital hard core interface timing fix
  • Multi voltage IO timing optimization
  • RDL power distribution optimization
Design Summary:
  • Process: 55nm LPE 1P7M
  • Gate count: 8M+ 200 Macro
  • Frequency: 400MHz
  • IP :
    • High-speed DSP
    • RF macro
    • Fractional PLL

Status: Mass Production

Design Challenges:
  • DDR interface
  • Noise reduction on RF interface
  • High-speed core optimization
  • Power shut-down by CPF/UPF flow

EE Solutions Service Offerings


Starting from the RTL design, through P&R implementation, to the final packaged and tested IC products, the company provides wide-range, flexible and multiple levels of service models (e.g., System Spec to ASIC production, RTL/Netlist to GDS, GDS to Wafer or Packaged IC). EE Solutions also allies with many design partners with a common goal to assist IC or Systems companies to accelerate their design completion. HDMI Tx/Rx, Ethernet 10/100M MAC/PHY, PCI Express PHY/Controller, USB 2.0 high-speed OTG, SerDes, etc. are some example IPs. Since established, EE Solutions has produced millions IC products for world-wide leading IC or System companies. The company is also reputable for its reliable and outstanding services.



  • RTL to mass production
  • Netlist to mass production
  • DFT/Scan insertion, JTAG insertion, ATPG, pattern simulation, MBIST
  • Hierachical Design Partitioning
  • STA
  • Physical synthesis
  • Clock tree synthesis
  • Place & Routing - single pass
  • Cross talk analysis and auto correction
  • Formal check
  • Layout Migration
  • Layout Verification
  • Timing Verification
  • Synthesis
  • Gate level timing verification
  • DFT/Scan insertion, JTAG insertion, ATPG, pattern simulation, MBIST
  • RTL design rule check - floating input/output, combinational loop clock report
  • Test vector conversion
  • IP development and integration
  • FPGA netlist converted to ASIC netlist - memory reconfiguration, cell conversion, etc.
  • Synthesis
  • Gate level timing verification
  • System architecture
  • Front-end design including digital RTL and analog design
  • Synthesis and DFT
  • Back-end process including AP&R, wafer process, testing, assembly
  • Logistics
  • Device driver development and even OS kernel porting